1. Field
Various features relate to a substrate that includes improved via pad placement in the bump area of the substrate.
2. Background
Current manufacturing techniques limit how closely traces, vias, and/or via pads can be close to each other. Because of these limitations in manufacturing techniques, dies and substrates have to be designed in a certain way. FIG. 1 illustrates how traces, vias and/or pads are implemented in current package substrates. Specifically, FIG. 1 illustrates a plan view (e.g., top view) of a package substrate 100 that includes a substrate 102, several bump pads (e.g., pads 104, 114), several traces (e.g., traces 106, 116) and several via pads (e.g., pad vias 108, 118). A bump pad is an interconnect that is configured to couple to a bump (e.g., copper pillar) from a die. The substrate 102 also includes several vias which are not visible from the plan view because these vias are covered by the via pads. These vias are coupled to the via pads. As further shown in FIG. 1, the bump pads, the via pads and/or traces are arranged in the package substrate 100 along different rows and columns. In some implementations, the package substrate 100 is configured to couple to one or more dies (e.g., flip chip).
Current manufacturing techniques create relatively large via pads (e.g., compared to the traces), which forces vias to be created towards the outer perimeter of a die coupling area of a package substrate. Moreover, current manufacturing techniques limit the pitch between traces, vias, bump pads and/or via pads. Because of these and other limitations in the manufacturing processes, a bump pad (e.g., pad 104) is coupled to a via pad (e.g., via pad 108) through a trace (e.g., trace 106). This design causes several problems. One, it creates an integrated circuit (IC) design that takes up a lot of real estate. Second, it creates performance issues, as the extra interconnect length (e.g., extra trace) can slow the electrical performance of the IC design. Three, adding additional interconnects (e.g., traces) creates a more complex IC design.
FIG. 2 illustrates a profile view (e.g., side view) of the cross-section AA of the package substrate 100 of FIG. 1. As shown in FIG. 2, the first pad 104 (e.g., bump pad), the first trace 106, and the second pad 108 (e.g., via pad) are on a first surface of the substrate 102. The package substrate 100 also includes a first via 208 that traverses the substrate 102. The first pad 104 is coupled to the first trace 106. The first trace 106 is coupled to the second pad 108. The second pad 108 is coupled to the first via 208. FIG. 2 also illustrates the third pad 114 (e.g., bump pad), the second trace 116, and the fourth pad 118 (e.g., via pad) are on the first surface of the substrate 102. The package substrate 100 also includes a second via 218 that traverses the substrate 102. The third pad 114 is coupled to the second trace 116. The second trace 116 is coupled to the fourth pad 118. The fourth pad 118 is coupled to the second via 218.
FIG. 3 illustrates how a flip chip may be coupled to a package substrate. As shown in FIG. 3, a flip chip 300 that includes a first bump 302 and a second bump 304, is coupled to the package substrate 100. The first bump 302 may include a first under bump metallization (UBM) layer, a first interconnect pillar (e.g., copper pillar), and a first solder ball. The second bump 304 may include a second under bump metallization (UBM) layer, a second interconnect pillar (e.g., copper pillar), and a second solder ball. The first bump 302 of the flip chip 300 is coupled to the first pad 104. The second bump 304 of the flip chip 300 is coupled to the third pad 114. As shown in FIG. 3, the configuration of the flip chip 300 and the package substrate 100 can create an unnecessary large package substrate 100 and/or flip chip 300. For example, there is a lot of excess lateral space/real estate between the first bump 302 and the first via 208.
Therefore, there is a need for an improved integrated device that is smaller and/or occupies a smaller real estate. Ideally, such an integrated device will have better performance than current integrated device.